1. Field of the Invention
The present invention relates generally to network communications. More specifically, the present invention relates to a clock recovery system.
2. Description of the Related Art
In electronics and especially synchronous digital circuits, a clock signal is a particular type of signal that oscillates between a high and a low state and is utilized like a metronome to coordinate actions of circuits. There are some instances, however, where a clock signal is not explicitly utilized. Some digital data streams, including, for example, high-speed data streams are sent without an accompanying clock signal. In such instances, the receiver must initiate some sort of clock recovery process to derive a clock signal from the data stream. This is because a serial data stream is merely a waveform representing a series of data symbols transmitted as sequential groups of symbols. The problem is that it is difficult to know at what instants it is best to sense or sample the signal. A clock signal must therefore be recovered from this sequential data. This process is commonly known as clock and data recovery (CDR).
Generally speaking, there are three current ways to perform CDR. The first is known as Phase-locked-loop-type (PLL-type). In PLL-type clock recovery, a control system generates an output signal whose phase is related to the phase of an input “reference” signal. The phase-locked-loop-type system includes a variable frequency oscillator, a filter and a phase detector. The phase of the input signal is compared with the phase of the signal derived from the output of the variable frequency oscillator and the system adjusts the frequency of the oscillator to keep the phases matched. The signal from the phase detector is used to control the oscillator in a feedback loop.
Frequency is the derivative of phase. Keeping the input and output phase in lock step implies keeping the input and output frequencies in lock step. Consequently, a phase-locked loop can track an input frequency, or it can generate a frequency that is a multiple of the input frequency.
FIG. 1 is a diagram of an exemplary PLL architecture. Included in the architecture are a phase detector 100, VCO 102, loop filter 104, and amplifier with gain K 106.
PLL-type clock recovery systems, however, have some drawbacks. First, they use a lot of power. In some circuits this is not an issue, but as power needs of circuits increase and size of circuits shrink, power usage becomes a larger concern. Additionally, PLL-type clock recovery systems require a lot of area. In the case of multiple receivers on the same chip, the architecture has a risk of coupling between voltage controlled oscillators (VCOs) which can result in clock jitter degradation.
The second way to perform CDR is to use a master clock to drive a phase interpolator. The phase interpolator generates multiple time-shifted phases of the master clock. Typically a PLL is used to implement a reference loop, which accepts an input reference clock signal and produces a set of high speed clock signals to be used as the reference phases. These references are then fed to a CDR loop that includes circuitry for continuously selecting reference phases and interpolating between them to provide clocks for recovering the data from the data signal. FIG. 2 is a diagram of an exemplary phase interpolator based CDR. Included in this clock recovery system is a reference loop 200 and a CDR loop 202. The CDR loop 202 includes a phase selector and interpolator 204, CDR loop control circuits 206, and samplers 208.
Unfortunately, in these types of systems, there are only a limited number of possible interpolated phases, leading to additional jitter degradation in the recovered clock. A further disadvantage of this scheme is that the output clock is always at the same frequency as the master clock. This means that there is always a steady state frequency mismatch in the received data and the recovered clock. This also means that, for the duration between control signal updates, the received clock is always accumulating phase error proportional to the integral of the frequency difference of the received data and the master clock.
The third way to perform CDR is to use an analog phase interpolator to generate a shifted clock using a control voltage as input. This scheme needs two voltages to be generated in response to the phase error, which are such that the sum of the squares of their amplitudes at all times is constant. FIG. 3 is a diagram of an exemplary data recovery circuit with analog phase interpolator. Here, both positive and negative transitions of the recovered clock are used for sampling. A preamplifier 300 is applied at the data input of the CDR to provide optimum common mode level for a phase detector 302 and to amplify the incoming data to increase the timing margin of the samplers. The phase of the recovered clock is adjusted in the phase interpolator core 304. Since the used binary phase detector samples the incoming data at its transition to derive the required phase information, two orthogonal, half-symbol shifted, clocks are provided by the PI core. The disadvantage here is that current implementations are analog in nature and hence tend to be approximations of what is really needed. Furthermore, despite the use of an analog PI, the phase adjustment of the recovered clock is not continuous. This is because the filter output changes in discrete steps.